1. Field of the Invention
This invention relates to a screen display device for displaying characters or patterns, such as a selected channel number, sound volume, or menu function (hereinafter collectively called "characters") on a TV screen.
2. Description of the Prior Art
FIG. 9 is a block diagram illustrating a configuration of a conventional screen display device. This screen display device is, for example, designed to have a display of 40 characters.times.3 lines on a single display screen. In FIG. 9, reference numeral 1 is a CPU (Central Processing Unit: processor), numeral 2 is an address bus and numural 3 is a data bus. Numeral 4 denotes a display memory in which code and display color data for each character or pattern to be displayed on a TV screen is stored and data is rewritten by the instruction of the CPU 1 and it is composed of RAM (Random Access Memory). Numerals 5 to 8 are circuits appendant to the display memory 4 which comprise: a first address decoder 5 which decodes an address signal outputted via the address bus 2 from the CPU 1, outputs the decoding result to the display memory 4 and designates a write address of the display memory 4: a write circuit for writing data (a given bit number of character code and color data) outputted via data bus 3 from the CPU 1 into an area shown by the write address which was designated by said first address decoder 5; a second address decoder 7 which decodes an address from a video signal output circuit 10 described below and designates a read address of the display memory 4: and a read circuit 8 for reading out data from the address designated by said second address decoder 7. Numeral 9 is a font memory composed of ROM (Read Only Memory) which prestores font data of characters or patterns to be displayed on the screen and from which the corresponding font data is read out in response to the character code read out from said display memory 4. A video signal output circuit is designated by numeral 10 and it reads out in sequence the data stored in said display memory 4 from a top of the address and outputs the data outputted from the font memory 9, i.e. font data, as video signal in accordance with the scanning line of a TV screen. The font data and the color data from the display memory 4 are inputted to the video signal output circuit and further a vertical synchronizing signal (VSYNC) from a terminal 11, a horizontal synchronizing signal (HSYNC) from a terminal 12 and a clock from a display oscillation circuit 13 are respectively inputted thereto and, based on these inputs, the font data is outputted as video signal to an output terminal of color signal output terminals 14 of R, G and B designated by the color data.
Then, the operation of the conventional device will be explained below. At first, character code and color data to be displayed on the TV screen are written to a display memory 4 by a program executable by a CPU 1. An addresss of the display memory 4 is outputted from CPU 1 to an address decoder 5 via an address bus 2 and data is outputted from CPU 1 to a write circuit 6 via a data bus 3.
When the character code having characters of 40 characters.times.3 lines, i.e. 120 characters (for example, 256 kinds of characters can be displayed for a character code of 8 bits) and color data (for example, 8 colors of display are possible for 3 bits of 1 bit each for R, G and B) are displayed on a single TV screen, as they have a one-to-one correspondence, it is necessary to write data to at least 120 bytes of the display memory 4 by the relation of one byte per one character in order to designate character code and color data corresponding to the single screen. As one byte of display memory 4 is accessed by one instruction executed by CPU 1, it is necessary for CPU 1 to execute 120 instructions in order to access all the data corresponding to 120 bytes. In this case, if total bit number for the character code and the color data is within 8 bits, it is possible to store one byte (8 bits) in one address by using CPU 1 of 8-bit bus configuration so that the character code and color data can be stored in the same address of the display memory 4. On the contrary, if the total bit number for the character code and color data is over 8 bits, they are respectively stored in the separate addresses of the display memory 4 and this means that write and read are controlled accordingly.
When setting of the character code and color data to the display memory 4 is completed by the execution of instruction of CPU 1, then the video signal output circuit 10 is formatted to start read-out from the top address of the display memory 4 by the vertical synchronizing signal (VSYNC) inputted via a terminal 11 from a synchronizing signal generation circuit of a TV. Further, a read-out address is supplied from the video signal output circuit 10 to the second address decoder 7 of the display memory 4 in synchronism with a horizontal scanning cycle of the horizontal synchronizing signal (HSYNC) from a terminal 12 and a clock of a display oscillation circuit 13, and the decoded result from the second address decoder 7 is supplied as the address of the display memory 4. The character code and color data previously set to the display memory 4 are read out in sequence in a character unit from a top of the address of the read circuit 8 according to the decoding result from the second address decoder 7. The read out color data is direct supplied to the video signal output circuit 10 to designate the R, G or B terminal of the color signal output terminals 14, but the character code is then supplied as the address of the font memory 9 and the data corresponding thereto, i.e. the font data previously written into the font memory 9 is read out and then inputted into the video signal output circuit 10. The video signal output circuit 10 synchronizes the font data with the horizontal synchronizing signal (HSYNC) from the terminal 12 and outputs the data in series, i.e. in sequence by one bit at a time from the color signal output terminals 14 corresponding to the color data previously read out, by the clock of the display oscillation circuit 13. The operation after the data is set in the display memory 4 is repeatedly performed in response to each vertical synchronizing signal (VSYNC) from the terminal 11 and as a result, the desired characters or patterns are displayed on the TV screen.
In such a conventional screen display device, as shown in FIG. 10(a) where all characters to be displayed on the screen are rewrited to be the same for one full line (includes the case where one blank line is made, i.e. a line is totally erased: see a first and second lines in this figure), where most characters are rewritten to have the same ones for a line except some (see a third line), or even in the case where characters in different colors are required to have the same colors as seen in FIG. 10(b), it has been necessary to access and rewrite all addresses of the display memory 4 corresponding to the characters to be displayed on the screen and further necessary for CPU to execute the number of instructions in response to the number of that access. Accordingly, the conventional screen device has problems in that too much load must be put on the software, a longer time is required to execute all the instructions and rewriting of the display characters are not efficiently performed.